Low power data-aware STT-RAM based hybrid cache architecture

@article{Imani2016LowPD,
  title={Low power data-aware STT-RAM based hybrid cache architecture},
  author={Mohsen Imani and Shruti Patil and Tajana S. Rosing},
  journal={2016 17th International Symposium on Quality Electronic Design (ISQED)},
  year={2016},
  pages={88-94}
}
Static Random Access Memories (SRAMs) occupy a large area of today's microprocessors, and are a prime source of leakage power in highly scaled technologies. Low leakage and high density Spin-Transfer Torque RAMs (STT-RAMs) are ideal candidates for a power-efficient memory. However, STT-RAM suffers from high write energy and latency, especially when writing `one' data. In this paper we propose a novel data-aware hybrid STT-RAM/SRAM cache architecture which stores data in the two partitions based… CONTINUE READING
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