Low power compression utilizing clock-gating

@article{Rajski2011LowPC,
  title={Low power compression utilizing clock-gating},
  author={Janusz Rajski and Elham K. Moghaddam and Sudhakar M. Reddy},
  journal={2011 IEEE International Test Conference},
  year={2011},
  pages={1-8}
}
Growing test data volume and excessive test power consumption in scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both scan shift and test response capture. Reducing the number of scan chains shifted during scan load can be expected to permit higher scan shift frequency thus reducing the… CONTINUE READING

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