Low-power bufferless resonant clock distribution networks

@article{Mesgarzadeh2007LowpowerBR,
  title={Low-power bufferless resonant clock distribution networks},
  author={Behzad Mesgarzadeh and Marcus Hansson and Atila Alvandpour},
  journal={2007 50th Midwest Symposium on Circuits and Systems},
  year={2007},
  pages={960-963}
}
The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed… CONTINUE READING

Figures, Results, and Topics from this paper.

Key Quantitative Results

  • Furthermore, in order to suppress large data-dependent jitter in bufferless network, injection-locking phenomenon is utilized to achieve about 40% peak-to-peak jitter reduction.
  • The 1.5-GHz LC resonator with on-chip inductance results in about 57% lower clock power and 20% lower total core power (with an effective tank quality factor of 3.6), while the 1.8-GHz and 1.1-GHz cores with off-chip inductors show about 64% and 73% lower clock power and 28% and 21% lower total core power, respectively.
  • To suppress the datadependent jitter an injection-locking-based technique has been used for achieving about 40% lower peak-to-peak jitter.

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References

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