Low-power array architectures for motion estimation

  title={Low-power array architectures for motion estimation},
  author={Leonel Sousa and Nuno Roma},
This paper proposes new eecient low-power systolic ar-chitectures for Full Search-Block Matching (FS-BM) motion estimation. These architectures allow to eliminate unnecessary computations, reducing the power consumption while preserving the optimal solution and the throughput. The new and traditional systolic architectures for motion estimation are compared in what concerns the required hardware and the power consumption. 
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Proc. of 1997 Int. Conf. on VLSI and CAD (ICVC)

  • K Parhi, low-Power Multimedia, Dsp Systems
  • Proc. of 1997 Int. Conf. on VLSI and CAD (ICVC)
  • 1997

\On the Development of a video CODEC for Low Bitrate Communication in General Purpose Computers

  • Sousa
  • Proc. of IASTED AI'99
  • 1997

\Image and Video Compression Standards, Algorithms and Architectures

  • V Bhaskaran, K Konstantinides
  • \Image and Video Compression Standards…
  • 1995

\VLSI Architectures for Video Compression{A Survey

  • P Pirsch, N Demassieux, W Gehrke
  • Proc. of the IEEE
  • 1995

\Motion Compensated Interframe Coding for Video Conferencing

  • T Koga
  • Proc. Nat. Telec. Conf
  • 1981

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