Low power and error resilient PN code acquisition filter via statistical error compensation

@article{Kim2011LowPA,
  title={Low power and error resilient PN code acquisition filter via statistical error compensation},
  author={Eric P. Kim and Daniel J. Baker and Sriram Narayanan and Douglas L. Jones and Naresh R. Shanbhag},
  journal={2011 IEEE Custom Integrated Circuits Conference (CICC)},
  year={2011},
  pages={1-4}
}
We present a 256-tap PN code acquisition filter in an 180nm CMOS process employing statistical system-level error compensation. Under voltage overscaling (VOS), near constant detection probability (Pdet) above 90% with 5.8× reduction in energy is achieved at a supply voltage 27% below the point of first failure (PoFF) with an error rate (pe) of 0.868. This is an improvement of 5.8× in energy-efficiency over conventional error free designs and 3.79× in energy-efficiency and 2170× in error… CONTINUE READING

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Key Quantitative Results

  • Under voltage overscaling (VOS), near constant detection probability (Pdet) above 90% with 5.8× reduction in energy is achieved at a supply voltage 27% below the point of first failure (PoFF) with an error rate (pe) of 0.868.

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