Low-power and error coding for network-on-chip traffic

  title={Low-power and error coding for network-on-chip traffic},
  author={Arseni Vitkovski and Raimo Haukilahti and Axel Jantsch and Emil Nilsson},
  journal={Proceedings Norchip Conference, 2004.},
The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay. 
7 Extracted Citations
14 Extracted References
Similar Papers

Citing Papers

Publications influenced by this paper.
Showing 1-7 of 7 extracted citations

Referenced Papers

Publications referenced by this paper.
Showing 1-10 of 14 references

Quality-of-Service end Error Control Techniques for Network-on-Chip Architectures

  • Praveen Vellanki
  • GLSVLSI’04, April 26-28,
  • 2004
3 Excerpts

A Survey of Techniques for Energy Efficient On-Chip Communication

  • Vijay Raghunathan
  • DAC 2003, June 2-6,
  • 2003
2 Excerpts

Modelling and Analysis of Interconnects for Deep Submicron Systems-on-Chip

  • Dinesh Pamunuwa
  • Doctoral Thesis, Royal Institute of Technology,
  • 2003

Nieuwland , Dietmar Muller , “ Why Transition Coding for Power Minimization of on - Chip Buses does not work ”

  • Claudia Kretzschmar, K Andre
  • 2003

Similar Papers

Loading similar papers…