Low-power VLSI decoder architectures for LDPC codes

  title={Low-power VLSI decoder architectures for LDPC codes},
  author={Mohammad M. Mansour and Naresh R. Shanbhag},
Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximum-likelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major challenge for building a practical low-power LDPC decoder. In this paper, we jointly design the code and the decoder to induce the structural regularity needed for a reduced complexity parallel decoder… CONTINUE READING
Highly Influential
This paper has highly influenced 12 other papers. REVIEW HIGHLY INFLUENTIAL CITATIONS
Highly Cited
This paper has 150 citations. REVIEW CITATIONS

12 Figures & Tables



Citations per Year

150 Citations

Semantic Scholar estimates that this publication has 150 citations based on the available data.

See our FAQ for additional information.