Low-power VLSI decoder architectures for LDPC codes

@inproceedings{Mansour2002LowpowerVD,
  title={Low-power VLSI decoder architectures for LDPC codes},
  author={Mohammad M. Mansour and Naresh R. Shanbhag},
  booktitle={ISLPED},
  year={2002}
}
Iterative decoding of low-density parity check codes (LDPC) using the message-passing algorithm have proved to be extraordinarily effective compared to conventional maximum-likelihood decoding. However, the lack of any structural regularity in these essentially random codes is a major challenge for building a practical low-power LDPC decoder. In this paper, we jointly design the code and the decoder to induce the structural regularity needed for a reduced complexity parallel decoder… CONTINUE READING
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