In this paper, the VLSI implementation of a low memory and low complexity architecture of JPEG2000 codec is presented. By analyzing the fix-point computation of discrete wavelet transform (DWT), a low memory implementation for lossy JPEG2000 codec is proposed. An efficient memory organization is adopted in this implementation to improve the speed of embedded block coding with optimized truncation (EBCOT) hardware accelerator. A buffered architecture is adopted in lifting based DWT to reduce the hardware cost, to achieve the higher hardware utilization and to reduce complexity of address generator. For EBCOT, a column-based coding of Tier-1 block coding engine and an effectively simplified Tier-2 coding engine are proposed. The proposed architecture of JPEG2000 codec is implemented in test camera chip that has been manufactured in 0.25um CMOS digital process. Index Terms — codec, discrete wavelet transform, embedded block coding with optimized truncation, JPEG2000, VLSI.