Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

@article{Andrieu2010LowLA,
  title={Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond},
  author={François Andrieu and Olivier Weber and J. Mazurier and Olivier Thomas and J-P. Noel and Claire Fenouillet-B{\'e}ranger and J-P. Mazellier and P. Perreau and T. Poiroux and Yves Morand and Thierry Morel and Stephane Allegret and V. Loup and S{\'e}bastien Barnola and François Martin and J-F. Damlencourt and Isabelle Servin and Mikael Casse and Xavier Garros and Olivier Rozeau and M-A. Jaud and Gerald Cibrario and Jacques Cluzel and Alain Toffoli and Fabienne Allain and Raphael Kies and Dominique Lafond and V. Delaye and Claude Tabone and L. Tosti and Laurent Brevard and Priya Gaud and Vamsi K. Paruchuri and K. K. Bourdelle and W. Schwarzenbach and O. Bonnin and B-Y. Nguyen and Bruce B. Doris and Fr{\'e}d{\'e}ric Boeuf and Thomas Skotnicki and Olivier Faynot},
  journal={2010 Symposium on VLSI Technology},
  year={2010},
  pages={57-58}
}
We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V<inf>T</inf>-variability performances are obtained (A<inf>VT</inf>=1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V<inf>DD</inf>=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ<inf>SNM</inf><SNM/6) down to V<inf>DD</inf>=0.7V. We also demonstrate ultra-low leakage (<0.5pA/µm… CONTINUE READING
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