Low-cost testing of high-density logic components


The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The… (More)
DOI: 10.1109/TEST.1989.82339


8 Figures and Tables

Slides referencing similar topics