Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions.

Abstract

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (Dit) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the… (More)
DOI: 10.1021/acs.nanolett.5b05253

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