Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

@article{Gierkink2008LowSpurLC,
  title={Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump},
  author={S. Gierkink},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={2967-2976}
}
  • S. Gierkink
  • Published 2008 in IEEE Journal of Solid-State Circuits
A clock multiplier combines the low reference spur of a PLL with the low phase noise of a recirculating DLL. It uses a ring oscillator that has two pulses running simultaneously that are phase independent. One pulse is used by a PLL to precisely set ring delay while the other pulse is periodically realigned with the reference phase by a process of pulse removal and reinsertion, similar to a DLL. The DLL reference spur due to static phase offset is eliminated, since the realigned pulse is not… CONTINUE READING
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A coupled sawtooth oscillator combining low jitter with high control linearity

  • S.L.J. Gierkink, A.J.M. van Tuijl
  • IEEE J. Solid-State Circuits, vol. 37, no. 6, pp…
  • 2002
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