Low Power and Energy Efficient Asynchronous Design

  title={Low Power and Energy Efficient Asynchronous Design},
  author={Peter A. Beerel and Marly Roncken},
  journal={J. Low Power Electron.},
This paper surveys the most promising low-power and energy-efficient asynchronous design techniques that can lead to substantial advantages over synchronous counterparts. Our discussions cover macro-architectural, micro-architectural, and circuit-level differences between asynchronous and synchronous implementations in a wide range of designs, applications, and domains including microprocessors, application specific designs, and networks on chip. 

Figures and Tables from this paper

Design of low-power low-area asynchronous iterative multiplier

Post-layout simulation results show that the asynchronous multiplier could provide a much faster average speed than synchronous approach and exhibits a prominent area reduction compared with other non-iterative multiplier bene fi ted from the iterative architecture.

High-Performance Asynchronous Pipelines: An Overview

This tutorial provides an overview of the best-in-class asynchronous pipelining methods that can be used to fully exploit the advantages of this design style, covering both static and dynamic logic implementations.

Energy and Performance Balancing Architecture for Asynchronous Data Processing Platforms

Simulation results and comparison with previously designed MTNCL homogeneous and heterogeneous platforms implementing only DVS show enhanced coherency between energy consumption and performance, and the improved effectiveness of DVS with core disabling in balancing the energy and performance of both platforms.

Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime

Asynchronous operation in the sub-threshold regime resulted in energy consumption savings of up to 51% on the ISCAS85 benchmark circuits synthesized in a digital CMOS 0.18 m process.

An innovative implementation of asynchronous for-loop circuit with click micropipeline

This paper proposes an asynchronous cycle circuit by providing Click element and joint module rather than clock-domain. The asynchronous mode of operation re-uses the simple asynchronous control

Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip

This work considers network-on-chip architectures partitioned into several voltage-frequency islands (VFIs) and proposes a design methodology for runtime energy management that minimizes the energy consumption subject to performance constraints.

The impact of voltage scaling over delay elements with focus on post-silicon tests

This work shows an analysis of delay elements behavior under voltage scaling and the impact on post-silicon tests and introduces a new term to determine the voltage scaling impact on delay elements and also the comparison between the most used DEs on BD designs using this novel metric.

Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study

A fully-decoupled latch controller has been developed, which integrates the current sensing circuitry and bundled-data circuitry and current sensing completion detection in the design of self-timed energy-minimum circuits, operating in the sub-VT domain.

On Dual-Rail Control Logic for Enhanced Circuit Robustness

An automated approach to synthesis of robust controllers for sub-threshold digital systems based on dual-rail implementation of control logic which eliminates inverters completely is presented and its properties are analysed and compared to the standard single-rail solutions.

Minimum-Energy SubThreshold Self-Timed Circuits : Design Methodology and a Case Study

This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current



VLSI Programming of Asynchronous Circuits for Low Power

In this chapter we analyze the potential of asynchronous circuits for low power consumption. We set out by reviewing the mechanisms of energy dissipation of digital CMOS ICs in general and clocked

Cell processor low-power design methodology

This work presents the basic methodology behind cycle-accurate power estimation, and forms a basis for explaining the techniques used to reduce power in the first-generation Cell processor, along with data that correlates the hardware measurements against power estimates.

Low-swing on-chip signaling techniques: effectiveness and robustness

This paper reviews a number of low-swing on-chip interconnect schemes and presents a thorough analysis of their effectiveness and limitations, especially on energy efficiency and signal integrity. In

Exploring Very Low-Energy Logic: A Case Study

Leakage is shown as a limit to the effectiveness of voltage scaling as a means of reducing the energy per operation in a digital circuit.

Asynchronous circuits for low power: a DCC error corrector

The authors describe a complete low-power digital compact cassette error corrector. Using Tangram, a high-level programming language, they designed two asynchronous circuits that correct errors on

An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

  • R. OzdagP. Beerel
  • Computer Science
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2006
This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates and highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on precharged half buffer (PCHB) templates.

An asynchronous low-power 80C51 microcontroller

This paper presents a low-power asynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 /spl mu/ CMOS process and it shows a power advantage of a factor 4 compared to a

Low-power network-on-chip for high-performance SoC design

An energy-efficient network-on-chip (NoC) is presented, which incorporates heterogeneous intellectual properties such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL) to achieve the power-efficient on-chip communications.

Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

The combination of supply scaling and self-timed circuitry which has some unique advantages, and the thorough analysis of the power savings that are possible using this technique are described.

Reconfigurable latch controllers for low power asynchronous circuits

Tests of the new latch controller circuits on a pipelined multiplier datapath show that reductions in energy per operation of up to 32% can be obtained by changing to the normally-closed operating mode.