Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
--A reliable low-power multiplier design by adopting algorithmic noise tolerant (ANT) architecture with truncated binary multiplier to build the fixed width reduced precision replica redundancy block (RPR). The ANT architecture can meet the high speed, low power, and area efficiency. To design the fixed-width RPR with error compensation circuit via analyzing of probability and statistics. Using this partial product terms of input correction vector and minor input correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified.