Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

@article{Arakali2009LowPowerST,
  title={Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture},
  author={Abhijith Arakali and Srikanth Gondi and P. K. Hanumolu},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={2169-2181}
}
A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in… CONTINUE READING
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