Low Voltage and Low Power in SRAM Read and Write Assist Techniques
- Dipti Choudhary, Vipul Bhatnagar
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.