Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture

  title={Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture},
  author={Yoonjin Kim and Rabi N. Mahapatra and Ilhyun Park and Kiyoung Choi},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of intellectual property (IP) cores. Reducing power is very crucial for CGRA to be more competitive and reliable… CONTINUE READING
Highly Cited
This paper has 30 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 18 extracted citations


Publications referenced by this paper.
Showing 1-10 of 22 references

Synopsys Corp. home page

  • Synopsys Corp., CA Mountain View
  • 2005. [Online]. Available: http://www.synopsys…
  • 2005
Highly Influential
7 Excerpts

Temporal mapping for loop pipelining on a mimd style coarse-grained reconfigurable architecture

  • J. W. Yoon, Y. Kim, M. Ahn, Y. Paek, K. Choi
  • presented at the Int. SoC Des. Conf., Seoul…
  • 2006
1 Excerpt

Dongbu Electronics home page

  • Dongbu Electronics, Seoul, Korea
  • 2005. [Online]. Available: http://www.dongbuelec…
  • 2005
1 Excerpt

Similar Papers

Loading similar papers…