Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture

@article{Kim2009LowPR,
  title={Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture},
  author={Yoonjin Kim and Rabi N. Mahapatra and Ilhyun Park and Kiyoung Choi},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2009},
  volume={17},
  pages={593-603}
}
Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of intellectual property (IP) cores. Reducing power is very crucial for CGRA to be more competitive and reliable… CONTINUE READING
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