Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

@article{Hwang2012LowPowerPF,
  title={Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme},
  author={Yin-Tsung Hwang and Jin-Fa Lin and Ming-Hwa Sheu},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2012},
  volume={20},
  pages={361-366}
}
In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an and function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor and gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse… CONTINUE READING

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