A 330Mhz 4–Way Superscalar Microprocessor
- David Greenhill, et.alii
- IEEE International Solid– State Circuits…
A method to reduce the power dissipated by PLAs is presented in . This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However,  concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power dissipated by static PLAs.