A method to reduce the power dissipated by PLAs is presented in [3]. This method is addressing both static and dynamic PLAs. The objective is to minimize the number of literals and product terms of a logic function. However, [3] concluded that the static power dissipation of the NOR gates is the dominant power dissipation, and the optimization proposed cannot decrease significantly the power dissipated by static PLAs.

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@inproceedings{Tavares2007LowPP, title={Low Power PLAs}, author={Reginaldo Tavares and Michel R. C. M. Berkelaar and Jochen A. G. Jess}, year={2007} }