Corpus ID: 85561522

Low Power Optimization Technique and a genetic minimization algorithm for variable ordering of BDD mapped VLSI Circuits

@inproceedings{Bansal2017LowPO,
  title={Low Power Optimization Technique and a genetic minimization algorithm for variable ordering of BDD mapped VLSI Circuits},
  author={M. Bansal and A. Agarwal},
  year={2017}
}
Ordered binary decision diagrams (BDDs) yield a data structure for switching functions that has been proven to be very useful in sloving many of the problems in VLSI CAD. BDDbased calculations is the variable ordering problem which addresses the major problem of finding an ordering of the input variables which minimizes the size of the BDD-representation. In this paper, the use of genetic algorithms to improve the variable ordering of a given BDD is implemented and experimental studies are… Expand

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References

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