Low Power Multipliers Using Enhenced Row Bypassing Schemes

  title={Low Power Multipliers Using Enhenced Row Bypassing Schemes},
  author={Yin-Tsung Hwang and Jin-Fa Lin and Ming-Hwa Sheu and Chia-Jen Sheu},
  journal={2007 IEEE Workshop on Signal Processing Systems},
In this paper, we proposed two novel low power multipliers based on enhanced row bypassing schemes. The essence of the power saving idea is eliminating unnecessary computation via signal bypassing. In an array multiplier, futile computations occur on those columns or rows of adder corresponding to zero bits in the input operands. Previous designs resort to input gating and output multiplexing to accomplish signal bypassing. The proposed designs, however, successfully resolve the adverse DC… CONTINUE READING

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