Low Power Multiplier Designs Based on Improved Column Bypassing Schemes

  title={Low Power Multiplier Designs Based on Improved Column Bypassing Schemes},
  author={Yin-Tsung Hwang and Jin-Fa Lin and Ming-Hwa Sheu and Chia-Jen Sheu},
  journal={APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems},
In this paper, we proposed two novel low power multiplier designs based on improved column bypassing schemes. The power saving comes from bypassing signals along those adder columns in the array multiplier corresponding to zero bits in the multiplicand. Spurious signal switching activities can then be eliminated when bypassing occurs. The proposed designs successfully resolve the adverse DC power consumption problem in previous research due to troublesome tri-state input buffers. Our designs… CONTINUE READING
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