Low Power Magnitude Comparator Circuit Design - Semantic Scholar

Abstract

This paper presents a new low power 2-Bit magnitude comparator using full adder technique. The proposed magnitude comparator (PTL logic) has been compared with existing magnitude comparator (GDI technique). The performance analysis of both magnitude comparators is done on basis of power consumption with respect to input voltage, temperature, and frequency… (More)

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Cited By

Design of low power 12-bit magnitude comparator

Dwip Narayan Mukherjee, Saradindu Panda, Bansibadan Maji
2017 Devices for Integrated Circuit (DevIC)
2017

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