Low Power Full Adder With Reduced Transistor Count
@inproceedings{Priya2013LowPF, title={Low Power Full Adder With Reduced Transistor Count}, author={M. Priya and K. Baskaran}, year={2013} }
Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic gate. This paper proposes a new 3T-XOR gate with significant area and power savings. In most of the digital systems adder lies in the critical path that increases the overall computational delay of the system. A new eight transistors one bit full adder based on 3T-XOR gate is presented. Simulations results utilizing standard 90nm CMOS technology illustrate a significant improvement in terms of number of… CONTINUE READING
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References
SHOWING 1-10 OF 10 REFERENCES
A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates
- Computer Science
- 2008
- 106
A novel hybrid pass logic with static CMOS output drive full-adder cell
- Computer Science
- Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03.
- 2003
- 166
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
- Engineering, Computer Science
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2006
- 390
- PDF
CMOS Digital Digital Integrated Circuits, Singapore
- Mc Graw Hill, 2nd edition,
- 1999