• Corpus ID: 12214933

Low Power Full Adder With Reduced Transistor Count

@inproceedings{Priya2013LowPF,
  title={Low Power Full Adder With Reduced Transistor Count},
  author={M. Geetha Priya and K. Baskaran},
  year={2013}
}
Basic building blocks of most of the arithmetic and logic circuits are formed by XOR logic gate. This paper proposes a new 3T-XOR gate with significant area and power savings. In most of the digital systems adder lies in the critical path that increases the overall computational delay of the system. A new eight transistors one bit full adder based on 3T-XOR gate is presented. Simulations results utilizing standard 90nm CMOS technology illustrate a significant improvement in terms of number of… 
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References

SHOWING 1-10 OF 11 REFERENCES

A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant…

A novel hybrid pass logic with static CMOS output drive full-adder cell

TLDR
A novel design of a 1-bit full adder cell featuring a hybrid CMOS logic style is proposed, which is very power efficient and has lower power-delay product over a wide range of voltages.

Low-voltage low-power CMOS full adder

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many…

Low-power logic styles: CMOS versus pass-transistor logic

TLDR
This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

A new design of the CMOS full adder

TLDR
By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder, and they have desirable transfer characteristics.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

TLDR
The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.

Mixed analog-digital VLSI devices and technology

Contents: Introduction: Mixed Analog-Digital Chips The MOSFET: Introduction and Qualitative View MOSFET DC Modeling MOSFET Small-Signal Modeling Technology and Available Circuit Components Layout…

Digital Integrated Circuits

TLDR
Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.

Principles of CMOS VLSI Design

  • 1985

CMOS Digital Digital Integrated Circuits, Singapore

  • Mc Graw Hill, 2nd edition,
  • 1999