Low-Power FinFET design schemes for NOR address decoders

@article{Turi2010LowPowerFD,
  title={Low-Power FinFET design schemes for NOR address decoders},
  author={Michael A. Turi and Josex0301 G Delgado-Frias and Niraj K. Jha},
  journal={Proceedings of 2010 International Symposium on VLSI Design, Automation and Test},
  year={2010},
  pages={74-77}
}
This paper presents and evaluates six novel, low-power, FinFET-based design schemes of the conventional NOR address decoder. These schemes differ in front- and back-gate connections and input signal swing. Simulations of these schemes were performed using a 32nm FinFET technology model and the schemes' performance was evaluated in terms of dynamic current consumption, delay, and leakage current consumption. The Low-Power (LP) scheme, a scheme where the FinFETs' back gates are reverse-biased for… CONTINUE READING