Low Power FPGA Architecture

  • Abhijeet Khandale
  • Published 2015

Abstract

A comprehensive analysis and implementation of FPGA architecture for low routing power and clock gated CLBs has been presented in this paper. The power consumption in FPGAs is more in routing and in clock network. As the FPGA has thousands of logic blocks and hard embedded micros spread across the FPGA chip, more numbers of routing lines and switch boxes… (More)

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