• Corpus ID: 2241382

Low Power Electronics and Design

@inproceedings{BlaauwLowPE,
  title={Low Power Electronics and Design},
  author={David Blaauw and Thaddeus J. Gabara and Guest Editor}
}

• D. Blaauw, T. Gabara, G. Editor
• Computer Science

L OW power design has played an important role in very large scale integration (VLSI) design, particularly as we continue to double the number of transistors on a die every two years and increase the frequency of operation. One important aspect of low power is mobile communications and its impact on our lives. We are at the start of the proliferation of mobile PDA's (Personal Digital Assistants), cellular phones, and portable computing. All of these devices are shaping the way we will be interacting with our family, peers, and workplace and require new and innovative low power design techniques. In addition, low power design techniques are becoming paramount in high performance desktop applications, such as high performance microprocessors, due to cooling and power supply integrity concerns. Hence, low power design can be expected to increase in its prominence as we move to next-generation designs. In all, 11 papers were accepted for this special issue, which were solicited from the Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'00). There are seven full papers and four brief papers. These papers were divided into two categories: 1) design tools, systems, and software and 2) architecture, circuits, and technology. The design tools, systems, and software section has four papers. The first paper by Kruse et al. describes a calculation of lower and upper bounds on the power consumption from scheduled data flow graphs. The second paper by Simunic et al. discusses low power hardware and software optimization for an embedded system. The last two papers are brief papers. The third paper is a brief by Martin et al. that explores different system level factors that affect the power-performance Publisher Item Identifier S 1063-8210(01)04463-8. tradeoff and then proposes a method for setting a low bound on CPU speed. The final paper is a brief by Leung et al. proposes a low power Turbo decoding approach a reduced number of iterations and dynamic voltage scaling. The architecture, circuits , and technology section has seven papers. The first full paper is by Muhammad et al. and describes a finite impulse response filter for magnetic recording. The second paper by Kim et al. discusses an adiabatic circuit technique with two times lower energy efficiency over previous work. The third paper by Meninger et al. covers a system that translates mechanical vibrations into electrical energy. The fourth paper by Powell et al. proposes to reduce …