Corpus ID: 212477431

Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics

@inproceedings{MahyarShahsavari2012LowPC,
  title={Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics},
  author={MahyarShahsavari},
  year={2012}
}
  • MahyarShahsavari
  • Published 2012
  • In a VLSI circuit, about 70 percent of area occupies by Interconnection. Such a large number of area occupation leads to many limitations of fabricating and applying in binary circuit implementation. Multiple-valued logic is one of the most proper way to improve the ability of value and data transferring in binary systems. Nowadays as small portable devices consuming are largely increased, applying low power approaches are considerably taking into account. In this paper we suggest and evaluate… CONTINUE READING
    19 Citations

    Tables from this paper

    CNTFET-based design of dynamic ternary full adder cell
    • 2
    Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs
    • 13
    Two state-of-the-arts current-mode ternary full adders based on CNTFET Technology
    A Novel CNTFET-based Ternary Full Adder
    • 55
    • Highly Influenced
    Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits
    • 33
    A Novel Low Power Ternary Multiplier Design using CNFETs
    • 1
    A CNTFET Based Quaternary Ful1 Adder
    DESIGN OF A THREE BIT TERNARY PREFIX ADDER USING CNFET
    • Lijitha Merin Jacob
    • 2019
    • PDF
    Dramatically Low-Transistor-Count High-Speed Ternary Adders
    • 22
    • PDF
    Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs
    • 8

    References

    SHOWING 1-10 OF 37 REFERENCES
    A novel CNTFET-based ternary logic gate design
    • 129
    • PDF
    High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder
    • 59
    • PDF
    CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits
    • 329
    • PDF
    Dynamic circuits for ternary computation in carbon nanotube based field effect transistors
    • K. Nepal
    • Materials Science
    • Proceedings of the 8th IEEE International NEWCAS Conference 2010
    • 2010
    • 14
    Carbon-nanotube-based voltage-mode multiple-valued logic design
    • 230
    A New CMOS Ternary Logic Design for Low-power Low-voltage Circuits
    • 10
    • PDF