• Corpus ID: 212477431

Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics

  title={Low Power CNTFET-Based Ternary Full Adder Cell for Nanoelectronics},
In a VLSI circuit, about 70 percent of area occupies by Interconnection. Such a large number of area occupation leads to many limitations of fabricating and applying in binary circuit implementation. Multiple-valued logic is one of the most proper way to improve the ability of value and data transferring in binary systems. Nowadays as small portable devices consuming are largely increased, applying low power approaches are considerably taking into account. In this paper we suggest and evaluate… 

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  • Kundan Nepal
  • Engineering
    Proceedings of the 8th IEEE International NEWCAS Conference 2010
  • 2010
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