Corpus ID: 15958423

Low Power CMOS Counter Using Clock Gated Flip-Flop

  title={Low Power CMOS Counter Using Clock Gated Flip-Flop},
  author={Upwinder Kaur and Rajesh Mehra},
gated flip-flop is presented in this paper. The circuit is based on a new clock gating flip flop approach to reduce the signal's switching power consumption. It has reduced the number of transistors. The proposed flip-flop is used to design 10 bits binary counter. This counter has been designed up to the layout level with 1V power supply in 90nm CMOS technology and have been simulated using Microwind simulations. Simulations have shown the effectiveness of the new approach on power consumption… Expand

Figures and Tables from this paper

In this paper design of synchronous 4-bit up counter is proposed using master-slave negative pulse-triggered D flip-flops and optimized layout of the counter is designed using Cadence Virtuoso Layout Suite. Expand
CMOS 8-bit Counter for ADC Application
In this paper design of synchronous 8-bit up counter is proposed. A counter can play an important role in several circuits such as in a simple display, microcontroller circuits etc. For counter,Expand
Design and Implementation of T-Flip Flop using GDI Techniques
Simulation results on 45nm technology show that the proposed T-flip flop has, the less circuit design area and prorogation delay of 67.35% and consumption power is 57.43% in a power supply of 1 V. Expand
Clock Gating: A Comprehensive Power Optimization Technique for Sequential Circuits
Low power is the most critical issues in today’s ASIC design, as the feature size is scaled down. Hence there is a urgent need for power optimization. Clock gating is one of the most elegant andExpand
Performance Evaluation of Ring Counter using Gated Clock
Minimizing Power dissipation is one of the major concerns in the VLSI industry.Due the rapid growth in technology, there is a tremendous reduction in the chip size. Minimum power consumption hasExpand
Low Power Clock Gated Sequential Circuit Design
Reducing Power dissipation is one of the crucial problems in today’s scenario. So this dissipation has become a bottleneck in the design of high speed synchronous systems which are operating at highExpand
Implementation of D Flip-Flop using CMOS Technology
This schematic of d flip flop has been designed and its equivalent layout is created using Micro wind tools and these proposed circuits are investigated in terms of area and power consumption and delay. Expand
Look Ahead Clock gating using an Auto gated Flip flop for Low Power Application
We propose new technique for clock gating. Clock gating is helpful for reducing power consumed in digital systems. There are three technique used, viz., (i) Synthesis Based method (ii) Data driverExpand
Johnson Counter Using Master Slave D Flip Flop
In a digital system the contribution of Sequential circuits is very large in terms of power dissipation and propagation delay. For VLSI back end designers maintaining low power with less delay andExpand
CMOS Technology for Increasing Efficiency of Clock Gating Techniques Using Tri-State Buffer
A comparative analysis of the new clock gating technique in an 8-bit Arithmetic Logic Unit (ALU) using tri-state buffer in a negative latch design, instead of OR gate logic, which provides a solution to the problems in the existing techniques. Expand


Low power flip-flop with clock gating on master and slave latches
A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomesExpand
Clock-gating and its application to low power design of sequential circuits
This paper models the clock behavior in a sequential circuit by a quaternary variable and uses this representation to propose and analyze two clock-gating techniques, which generate a derived clock synchronous with the master clock. Expand
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF canExpand
Gated-Clock Design of Linear-Feedback Shift Registers
  • W. Aloisi, R. Mita
  • Computer Science
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2008
The proposed scheme is based on the gated clock design approach and it can offer a significant power reduction, depending on technological characteristics of the employed gates, as well as validate through many transistor-level SPECTRE simulations in CADENCE environment. Expand
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design
An adaptive clock gating (ACG) technique which can be easily realized is introduced for the low power IP core design and can automatically enable or disable the IP clock to reduce not only dynamic power but also leakage power with power gating technique. Expand
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
Applying clock gating to the energy recovery clocked flip-flops reduces their power by more than 1000times in the idle mode with negligible power and delay overhead in the active mode. Expand
Low power flip-flop with clock gating on master and slave latches
I Conclusion: In this Letter, we have shown that the method proposed in [2] could be used even in the case where non-neglectible values of feedback delay are encountered. A very interestingExpand
A Data-transition Look-ahead DFF Circuit For Statistical Reduction In Power Consumption
  • Nogawa, Ohtomo
  • Engineering
  • Symposium 1997 on VLSI Circuits
  • 1997
A new data-transition look-ahead DFF (DL-DFF) that reduces the power consumption of CMOS LSI's is proposed. The power consumption is reduced in accordance with the data-transition probability. TheExpand
Nonredundant successive approximation register for A/D converters
A successive approximation register for N bit A/D converters is presented. It code the possible 2/sup N/ conversion output values with the minimum number FF (log/sub N/). As it is nonredundant andExpand
A sub-1V bootstrap pass-transistor logic
  • IEICE Trans. Electronics, E86-C, (4), pp. 604-611, 2000.
  • 2000