Corpus ID: 15958423

Low Power CMOS Counter Using Clock Gated Flip-Flop

@inproceedings{Kaur2013LowPC,
  title={Low Power CMOS Counter Using Clock Gated Flip-Flop},
  author={Upwinder Kaur and Rajesh Mehra},
  year={2013}
}
  • Upwinder Kaur, Rajesh Mehra
  • Published 2013
  • Engineering
  • gated flip-flop is presented in this paper. The circuit is based on a new clock gating flip flop approach to reduce the signal's switching power consumption. It has reduced the number of transistors. The proposed flip-flop is used to design 10 bits binary counter. This counter has been designed up to the layout level with 1V power supply in 90nm CMOS technology and have been simulated using Microwind simulations. Simulations have shown the effectiveness of the new approach on power consumption… CONTINUE READING

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