Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder

@article{Zhang2013LowLatencySA,
  title={Low-Latency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder},
  author={Chuan Zhang and Keshab K. Parhi},
  journal={IEEE Transactions on Signal Processing},
  year={2013},
  volume={61},
  pages={2429-2441}
}
Polar codes have recently emerged as one of the most favorable capacityachieving error correction codes due to their low encoding and decoding complexity. However, because of the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only high hardware cost but also long decoding latency. In this paper, a data-flow graph (DFG) for the SC decoder is derived. A complete hardware architecture is first… CONTINUE READING
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VLSI Digital Signal Processing Systems: Design and Implementation

  • K. K. Parhi
  • 1999
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