Low-Jitter Clock Multiplication : A Comparison Between PLLs and DLLs

  title={Low-Jitter Clock Multiplication : A Comparison Between PLLs and DLLs},
  author={Remco van de Beek and Eric A. M. Klumperink and Cicero S. Vaucher and Bram Nauta},
This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic… CONTINUE READING
Highly Cited
This paper has 60 citations. REVIEW CITATIONS


Publications citing this paper.
Showing 1-10 of 44 extracted citations

61 Citations

Citations per Year
Semantic Scholar estimates that this publication has 61 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 19 references

Timing jitter analysis for highfrequency, low-power CMOS ring-oscillator design

  • T. C. Weigandt, B. Kim, P. R. Gray
  • presented at the Proc. Int. Symp. Circuits and…
  • 1994
Highly Influential
4 Excerpts

Low - power small - area  7 . 28 ps jitter 1 GHz DLL - based clock generator , ” in

  • P. R. Gray
  • Proc . SSCC Dig . Tech . Papers , Feb .
  • 2002

Similar Papers

Loading similar papers…