Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction

@article{Zadeh2013LowDH,
  title={Low Dit high-k/In0.53Ga0.47As gate stack, with CET down to 0.73 nm and thermally stable silicide contact by suppression of interfacial reaction},
  author={Davood Hassan Zadeh and H. Oomine and Kuniyuki Kakushima and Yoshinori Kataoka and Akira Nishiyama and Nobuyuki Sugii and Hitoshi Wakabayashi and Kazuo Tsutsui and Kenji Natori and Hiroshi Iwai},
  journal={2013 IEEE International Electron Devices Meeting},
  year={2013},
  pages={2.4.1-2.4.4}
}
Ultra-thin InGaAs gate stacks with CET= 0.73 nm (EOT<; 0.5 nm), D<sub>it</sub> as low as 8.0×10<sup>11</sup> (cm<sup>-2</sup> eV<sup>-1</sup>) and thermal stability up to 600°C is demonstrated by using La<sub>2</sub>O<sub>3</sub> as gate dielectric. A silicide/InGaAs junction with excellent controllability at the interface is also proposed. These results promise the integration compatibility of this gate stack for future node 3D device structures.