Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$ Root and $N^{th}$ Power Computations

@article{Mopuri2019LowCG,
  title={Low Complexity Generic VLSI Architecture Design Methodology for \$N^\{th\}\$ Root and \$N^\{th\}\$ Power Computations},
  author={Suresh Mopuri and Amit Acharyya},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2019},
  volume={66},
  pages={4673-4686}
}
  • Suresh MopuriA. Acharyya
  • Published 16 September 2019
  • Computer Science
  • IEEE Transactions on Circuits and Systems I: Regular Papers
In this paper, we propose a low complexity architecture design methodology for fixed point root and power computations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and… 

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers

A methodology for performing root computations on floating-point numbers based on the piecewise linear (PWL) approximation method and determines the widest segments of the subtasks and the smallest fractional width needed to satisfy the predefined maximum relative error.

Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions

A symmetric-mapping lookup table (SM-LUT) to be capable of computing inline-formula functions and an optimized Vedic multiplier to shorten the critical path and improve the efficiency of multiplication are used.

Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

A low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC), independent of angle computation in the CORDIC unlike the state-of-the-art methodologies.

Low-Latency and Minor-Error Architecture for Parallel Computing XY-like Functions with High-Precision Floating-Point Inputs

This paper employs two specific techniques to enlarge the range of convergence of the QH CORDIC, making it possible to deal with high-precision floating-point inputs, and shows that the proposed architecture has 30 more orders of magnitude of maximum relative error and average relative error than the state-of-the-art.

References

SHOWING 1-10 OF 23 REFERENCES

Low-Complexity Methodology for Complex Square-Root Computation

A low-complexity methodology to compute a complex square root using only a circular coordinate rotation digital computer (CORDIC) as opposed to the state-of-the-art techniques that need both circular as well as hyperbolic CORDICs is proposed.

Coordinate Rotation-Based Design Methodology for Square Root and Division Computation

The proposed methodology eliminates the requirement of a separate hardware for square root and division computation in the CORDIC-based applications without compromising the computational speed, throughput and accuracy.

CORDIC-Based Architecture for Computing Nth Root and Its Implementation

This paper presents a COordinate Rotation Digital Computer (CORDIC)-based architecture for the computation of Nth root and proves its feasibility by hardware implementation and develops a flexible architecture in terms of convergence range and precision.

High-radix iterative algorithm for powering computation

A sequential implementation of the algorithm is proposed, and the execution times and hardware requirements are estimated for single and double-precision floating-point computations, for radix r=128, showing that powering can be computed with similar performance as high-radix CORDIC algorithms.

Composite Iterative Algorithm and Architecture for q-th Root Calculation

A detailed error analysis and two architectures are proposed, for low precision q and for higher precision q, based on an optimized implementation of X^{1/q} by a sequence of parallel and/or overlapped operations.

Floating-Point Exponentiation Units for Reconfigurable Computing

The implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes is studied.

Concept, Design, and Implementation of Reconfigurable CORDIC

This brief presents the key concept, design strategy, and implementation of reconfigurable coordinate rotation digital computer (CORDIC) architectures that can be configured to operate either for

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

A pipeline hyperbolic CORDIC processor to implement a direct digital synthesizer (DDS) and an efficient arbitrary waveform generator (AWG), where a pseudo-random number generator modulates the linear increments of phase to produce random phase-modulated waveform.

Experiments with High Speed Parallel Cubing Units

The method proposed in this paper separates the cubing partial product matrix into smaller elements and organizes these partial products into repeatable manageable groups so that the overall partial products matrix is substantially reduced from previous methods.

50 Years of CORDIC: Algorithms, Architectures, and Applications

A brief overview of the key developments in the CORDIC algorithms and architectures along with their potential and upcoming applications is presented.