Low Complexity Generic VLSI Architecture Design Methodology for $N^{th}$ Root and $N^{th}$ Power Computations

  title={Low Complexity Generic VLSI Architecture Design Methodology for \$N^\{th\}\$ Root and \$N^\{th\}\$ Power Computations},
  author={Suresh Mopuri and A. Acharyya},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  • Suresh Mopuri, A. Acharyya
  • Published 2019
  • Mathematics, Computer Science
  • IEEE Transactions on Circuits and Systems I: Regular Papers
In this paper, we propose a low complexity architecture design methodology for fixed point root and power computations. The state of the art approaches perform the root and power computations based on the natural logarithm-exponential relation using Hyperbolic COordinate Rotation DIgital Computer (CORDIC). In this paper, any root and power computations have been performed using binary logarithm-binary inverse logarithm relation. The designs are modeled using VHDL for fixed point numbers and… Expand
2 Citations
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers
Symmetric-Mapping LUT-Based Method and Architecture for Computing XY-Like Functions


Low-Complexity Methodology for Complex Square-Root Computation
Coordinate Rotation-Based Design Methodology for Square Root and Division Computation
CORDIC-Based Architecture for Computing Nth Root and Its Implementation
High-radix iterative algorithm for powering computation
Composite Iterative Algorithm and Architecture for q-th Root Calculation
Floating-Point Exponentiation Units for Reconfigurable Computing
Power Efficient Division and Square Root Unit
Concept, Design, and Implementation of Reconfigurable CORDIC
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation
Experiments with High Speed Parallel Cubing Units