Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects

@inproceedings{Roy1994LogicSF,
  title={Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects},
  author={Kaushik Roy and Sharat Prasad},
  booktitle={EURO-DAC},
  year={1994}
}
Designing reliable CbfOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier effects. This paper considers logic synthesis to handle electromigration and hot carrier degmdation early in the design phase. The electromigration and the hot carier eflecls are estimated at the gate level using signal activity measure, mhich is the avemge number of tmnsitions at circuit nodes. Logic can be optimally… CONTINUE READING