Logic rectification and synthesis for engineering change

Abstract

| In the process of VLSI design, specications are often changed. It is desirable that such changes will not lead to a very di erent design, so that a large part of engineering e ort can be preserved. We treat this problem as a combination of multiple{error diagnosis and logic minimization problems. Given a new speci cation and an existing synthesized logic… (More)
DOI: 10.1145/224818.224913

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