Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (VCC) ranging from 0.5v to 1.0v

  title={Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (VCC) ranging from 0.5v to 1.0v},
  author={Gilbert Hillsboro Dewey and Roza Kotlyar and Ravi Pillarisetty and Marko Radosavljevic and Titash Rakshit and Han Wui Then and Robert S. Chau},
  journal={2009 IEEE International Electron Devices Meeting (IEDM)},
  • G. DeweyR. Kotlyar R. Chau
  • Published 1 December 2009
  • Physics
  • 2009 IEEE International Electron Devices Meeting (IEDM)
In this paper for the first time, the logic performance of Schottky-gate In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V<inf>eff</inf>) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V<inf>eff</inf> enables 65% intrinsic drive current gain at V<inf>CC</inf> = 0.5V and… 

Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering Supply Voltage and OFF-Current

Comprehensive performance benchmarking results for III-V and Si nanowire nMOSFETs (gate length of 13 nm) are reported based on the atomistic full-band ballistic quantum transport simulation including

Performance Comparisons of III–V and Strained-Si in Planar FETs and Nonplanar FinFETs at Ultrashort Gate Length (12 nm)

The exponential miniaturization of Si complementary metal-oxide-semiconductor technology has been a key to the electronics revolution. However, the downscaling of the gate length becomes the biggest

High-Performance InAs Gate-All-Around Nanowire MOSFETs on 300 mm Si Substrates

We report on the first realization of InAs n-channel gate-all-around nanowire MOSFETs on 300 mm Si substrates using a fully very large-scale integration (VLSI)-compatible flow. Scaling of the

Contact modeling and analysis of InAs HEMT transistors

Novel device concepts and better channel materials than Si are required to improve the performance of conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). The exploration of

Interface-Trap Effects in Inversion-Type Enhancement-Mode $\hbox{InGaAs/ZrO}_{2}$ N-Channel MOSFETs

Interface-trap effects are analyzed in inversion-type enhancement-mode In0.53Ga0.47/ZrO2 and In0.53Ga0.47As/In0.2Ga0.8As/ZrO2 n-channel MOSFETs by comparing the measurements and the numerical device

Comparison of raised source/drain Implant-Free Quantum-Well and Tri-gate MOSFETs using 3D Monte Carlo simulation

  • E. TowieC. RiddetA. Asenov
  • Engineering
    2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)
  • 2013
In this paper we examine the impact of a raised source/drain architecture on the performance of single-gate and multi-gate, high mobility channel MOSFETs. We make use of 3D Monte Carlo (MC)

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

Author(s): Jacobson, Zachery Aaron | Advisor(s): King Liu, Tsu-Jae | Abstract: Continuing scaling of transistors as density approaches the terascale regime (1012 devices/cm2) requires evaluating new

III–V compound semiconductors for mass-produced nano-electronics: theoretical studies on mobility degradation by dislocation

In order for III–V compound MOSfETs to outperform silicon MOSFETs, Fermi level pinning in the channel should be eliminated for yielding carriers with high injection velocity.

Temperature Dependence of the Transconductance in Ballistic III–V QWFETs

The temperature dependence of the transconductance in III-V quantum well field-effect transistors is studied using 2-D ballistic device simulations. It is found that the experimental characteristics

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

DC and high-frequency device characteristics of In<sub>0.7</sub>Ga<sub>0.3</sub>As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art

On experimental determination of carrier velocity in deeply scaled NMOS: how close to the thermal limit?

Continued success in scaling bulk MOSFETs has brought increasing focus on fundamental performance limits. It has been proposed that drain current is ultimately limited by the rate at which carriers

Relationship between measured and intrinsic transconductances of FET's

In exploratory study of FET's, such as the study of deep-submicrometer-channel FET's, carrier transport quantities are extracted from the measured transconductance of a FET. The extraction requires


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