Logic masking for SET Mitigation Using Approximate Logic Circuits

  title={Logic masking for SET Mitigation Using Approximate Logic Circuits},
  author={Antonio Sanchez-Clemente and Luis Entrena and Mario Garc{\'i}a-Valderas and Celia L{\'o}pez-Ongil},
  journal={2012 IEEE 18th International On-Line Testing Symposium (IOLTS)},
Logic masking approaches for Single-Event Transient (SET) mitigation use hardware redundancy to mask the propagation of SET effects. Conventional techniques, such as Triple-Modular Redundancy (TMR), can guarantee full fault coverage, but they also introduce very large overheads. Alternatively, approximate logic circuits can provide the necessary flexibility to find an optimal balance between error coverage and overheads. In this work, we propose a new approach to build approximate logic… CONTINUE READING
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