Logic Synthesis for Engineering Change

Abstract

| In the process of VLSI design, speci cations are often changed. It is desirable that such changes will not lead to a very di erent design so that a large part of engineering e ort can be preserved. We consider synthesis algorithms for handling such engineering changes. Given a synthesized network, our algorithm modi es it minimally to realize a new speci cation.

DOI: 10.1145/217474.217604

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@article{Lin1995LogicSF, title={Logic Synthesis for Engineering Change}, author={Chih-Chang Lin and Kuang-Chien Chen and Shih-Chieh Chang and Malgorzata Marek-Sadowska and Kwang-Ting Cheng}, journal={IEEE Trans. on CAD of Integrated Circuits and Systems}, year={1995}, volume={18}, pages={282-292} }