Logic BIST with scan chain segmentation

  title={Logic BIST with scan chain segmentation},
  author={Liyang Lai and Janak H. Patel and Thomas Rinderknecht and Wu-Tung Cheng},
  journal={2004 International Conferce on Test},
This work presents a novel BIST (built-in self test) scheme with scan chain segmentation. In the scheme, a combination of pseudo random patterns and single-weight patterns have been applied to CUT (circuit under test). Scan chain is partitioned into multiple segments delimited by inverters. When a single weighted pattern is applied to a segmented scan chain, successive segments receive bit patterns with complementary weights. Several segment configurations may be required to achieve full fault… CONTINUE READING
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