Locating logic design errors via test generation and don't-care propagation

@inproceedings{Kuo1992LocatingLD,
  title={Locating logic design errors via test generation and don't-care propagation},
  author={Sy-Yen Kuo},
  booktitle={EURO-DAC},
  year={1992}
}
This paper presents a new technique, the don’t-care propagation method, for logic verification and design error location in a circuit. Test patterns for single stuck-line faults are used to compare the gate-level implementation of a circuit with its functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits… CONTINUE READING

Similar Papers

Loading similar papers…