Locating Functional Errors in Logic Circuits

  title={Locating Functional Errors in Logic Circuits},
  author={Koichiro Tamura},
  journal={26th ACM/IEEE Design Automation Conference},
  • K. Tamura
  • Published 1989
  • Computer Science
  • 26th ACM/IEEE Design Automation Conference
In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. In this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. The indicated areas are shown to have sufficient resolution to allow the designer to quickly find the… Expand
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