Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits

@article{Dhillon2005LoadAL,
  title={Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits},
  author={Yuvraj Singh Dhillon and Abdulkadir Utku Diril and Abhijit Chatterjee and Cecilia Metra},
  journal={11th IEEE International On-Line Testing Symposium},
  year={2005},
  pages={35-40}
}
Technology scaling has led to reduced noise margins and increased susceptibility of logic circuits to transient errors. In this paper, a novel methodology to increase the robustness of combinational circuits to transient errors is proposed. The number of errors propagated to the primary outputs (POs) is minimized by adding optimal amounts of capacitive loading to the POs of the logic circuit. Using a novel delay-assignment-variation (DAV) based optimization methodology, the sizes, supply… CONTINUE READING
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