Load Cache


As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the eeects of memory access latency. In this paper, we introduce a novel modiication of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the eeect of delays caused by the… (More)


Cite this paper

@inproceedings{Tyson1997LoadC, title={Load Cache}, author={Gary S. Tyson and Todd M. Austin}, year={1997} }