Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability


Technology scaling has brought about sub-wavelength lithography. Sub-wavelength lithography requires resolution enhancement techniques (RETs) including significant layout constraints and manufacturability verification using lithography simulation. Despite the use of these techniques, the design iterations may take too long and may not converge. In standard cell based designs, inter-feature interactions across abutting standard cells can result in reduced design and parametric yield. In this paper, we propose a litho aware design methodology that aims at fixing the violations due to standard cell abutments. The major contributions of this work are a phased approach towards elimination of lithography violations by 1) Pre-characterization of abutments for early detection of violations, 2) Iterative changes to placement to minimize violations and 3) SRAF insertion rules to eliminate violations. Experimental results on ISCAS and AES benchmark circuits show that the proposed methodology eliminates all lithography violations with no impact on area and minimal impact on performance.

DOI: 10.1109/ISVLSI.2011.32

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@article{Dhumane2011LithographyCP, title={Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability}, author={Nishant Dhumane and Sudheendra K. Srivathsa and Sandip Kundu}, journal={2011 IEEE Computer Society Annual Symposium on VLSI}, year={2011}, pages={200-205} }