Lino: a tiling language for arrays of processors

Abstract

Moore’s Law implies that as the scale of transistors shrinks, the number of gates that can be fitted onto a chip of a standard size, say of the order of 1cm, will double every two years. Historically this has been used by processor manufactures to increase the complexity of individual processor cores. The word length has grown from 4 bits in the first chips… (More)

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