Linearized Di erential Transconductors in Subthreshold CMOS

Three schemes for linearizing the transconductance of the basic di erential pair in subthreshold CMOS are examined: 1) multiple asymmetric di erential pairs, 2) source degeneration via symmetric di usors, and 3) source degeneration via a single di usor. Using a maximally at optimizing criterion, the linear range of the basic di erential pair can be… (More)