Line rate programmable packet processing in 100Gb networks


The P4 language provides a way to describe a custom network packet processing behavior that involves header parsing, matching and assembling modified packets. Such abstraction represents a significant step towards removing the limitation of fixed-function networking devices. Our live demonstration shows a straightforward usage of an algorithm and tool that maps a P4 program to a general architecture of FPGA-based networking device. Network traffic is received, parsed, filtered and modified by the generated circuit at the full line rate of 100 Gbps Ethernet. The results of our ongoing joint research project NFV200 show that the FPGA technology can be used to improve network flexibility without the usual burden of tedious and error-prone HDL coding.

DOI: 10.23919/FPL.2017.8056835

Cite this paper

@article{Bencek2017LineRP, title={Line rate programmable packet processing in 100Gb networks}, author={Pavel Ben{\'a}cek and Viktor Pus and Jan Korenek and Michal Kekely}, journal={2017 27th International Conference on Field Programmable Logic and Applications (FPL)}, year={2017}, pages={1-1} }