Limitations of incremental signal-tracing for FPGA debug

Abstract

Developing state-of-the-art custom silicon can be a prohibitively expensive and risky undertaking, due in no small part to the need to perform thorough design verification. Field-Programmable Gate-Arrays offer a flexible platform for constructing prototypes to aid in their verification, but unlike software simulation, observability into these prototypes is a major challenge. Designers can choose to insert trace-instrumentation to enhance on-chip observability, but doing so often requires re-compiling the entire design for each new trace configuration. This work presents two contributions: to explore the limitations of incremental-synthesis for trace-buffer insertion, and to propose CAD optimizations exclusive to this application for improving runtime and routability. We find that 99.4% of all used cluster outputs (driving both combinational and sequential circuit signals) can be incrementally-traced to 75% of the free memory-capacity on an FPGA, an order of magnitude quicker than the original compilation and with a nominal impact on circuit delay, for a 20% minimum channel width (10% area) increase.

DOI: 10.1109/FPL.2012.6339240

Extracted Key Phrases

11 Figures and Tables

Cite this paper

@article{Hung2012LimitationsOI, title={Limitations of incremental signal-tracing for FPGA debug}, author={Eddie Hung and Steven J. E. Wilton}, journal={22nd International Conference on Field Programmable Logic and Applications (FPL)}, year={2012}, pages={49-56} }