Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm


Implementation of low energy, low latency transmission line interconnects on a network-on-chip presents the circuit designer with a variety of structural design choices. This work presents a study of the comparative effects of changing the wire geometries on the latency, energy dissipated, area, and noise properties of the transmission lines. These results… (More)
DOI: 10.1109/NoCS.2013.6558408


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