Leveraging reconfigurability to raise productivity in FPGA functional debug

Abstract

We propose new hardware and software techniques for FPGA functional debug that leverage the inherent reconfigurability of the FPGA fabric to reduce functional debugging time. The functionality of an FPGA circuit is represented by a programming bitstream that specifies the configuration of the FPGA's internal logic and routing. The proposed methodology… (More)

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Cite this paper

@article{Poulos2012LeveragingRT, title={Leveraging reconfigurability to raise productivity in FPGA functional debug}, author={Zissis Poulos and Yu-Shen Yang and Jason Helge Anderson and Andreas G. Veneris and Bao Le}, journal={2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2012}, pages={292-295} }